1. Field of the Invention
The present invention relates generally to a microprogram control device, and more particularly, to a microprogram control device used in a computer, for example, a microcomputer or microprocessor.
2. Related Art
Many microcomputers employ a microprogram control device or system. An example of a conventional microprogram control device is shown in FIG. 5. A machine instruction code from a program memory (not shown) or the like is directly input to an address register 101. This address register 101 produces an output of 8 bits, which are high-order bits of a microcode address. A counter 102, reset in synchronism with the fetch of the machine instruction code sent to the register 101, produces an output of 4 bits, which are low-order bits of the microcode address.
These two outputs constituting the microcode address are input to an address decoding area 103a, which is part of a microcode storage unit 103, and can be in the form of, for example, a PLA (programmable logic array). The address decoding area 103a of microcode storage unit 103 decodes the input microcode address, causing a microcode stored in the addressed segment of a microcode memory area 103b to be output to a microinstruction register 104. Next, the contents of the counter 102 are incremented without altering the contents of the address register 101, thus causing sequential microcode addresses to be designated.
The conventional microcode storage unit 103 is configured as shown in FIG. 6. The address decoding area 103a has a series of microcode addresses. Each microcode address has, for example, 12 bits. Associated with each microcode address is a microcode of; for example, 21 bits, which microcode is stored within the microcode memory area 103b.
As seen from FIG. 6. with respect to four machine instructions of INC, MOV, SHIFT and ADD, a microprogram having microcodes of 2 steps are stored for machine instruction MOV, and microcodes of 3 steps are stored for machine instructions INC, SHIFT, and ADD, respectively.
More particularly, with respect to the INC instruction, the microprogram having three microcodes of "aa . . . a", "bb . . . b", and "cc . . . c" is stored. With respect to the MOV instruction, the microprogram having two microcodes of "dd . . . d" and "ee . . . e" is stored. Further, with respect to the SHIFT instruction, the microprogram having three microcodes of "aa . . . a", bb . . . b", and "cc . . . c" identical to the three microcodes of the INC instruction, is stored. In addition, with respect to the ADD instruction, the microprogram having three microcodes of "xx . . . x", "yy . . . y", and "zz . . . z" is stored. Note that areas represented by "** . . . *" are unnecessary memory areas since no microcodes for the given machine instruction microprogram need to be stored in these unused memory areas.
The above-mentioned conventional microprogram control device is required to produce a microprogram for each machine instruction. To create the low-order bits of the microcode address, counter 102 is used. Counter 102 is reset for each fetch of a machine instruction being called. By incrementing this counter, microcodes corresponding to each instruction are accessed in sequence from the start address of the microprogram being outputted. With the address decoder as employed in the above-mentioned conventional microcodes control device, the microstep is fixed to a preselected number of steps, for example, four steps. When machine instructions have microprograms with steps which are not multiples of the preselected number of steps (for example, integers of four steps), there is unused area in memory, which results in increased chip area.
Another example of a conventional microprogram control device will be described with reference to FIG. 7.
A machine instruction is decoded by machine instruction decoding circuit 110. Circuit 110 is typically comprised of PLA, such that microinstruction addresses from circuit 110 are input to a next microinstruction address determination circuit ill. A next microinstruction address output by circuit 111 is input to a control memory or store 112 and to an address converter 114.
Control memory 112 then outputs a microinstruction address to a microinstruction register 113. This microinstruction register 113 comprises a conditional branch instruction 113b, and another instruction 113a. To execute conditional branch instruction 113b, a control memory address, (that is, the next microinstruction address of the concerned microinstruction) is first converted into a nanoinstruction address by address converter 114. The nanoinstruction is then stored in nanoinstruction register 115.
Microinstruction 113a has an NMA (next microinstruction address) field that represents an address of the next microinstruction. When a TY field represents "00", the NMA field is output to the microinstruction address bus 120. When the TY field represents a value other than "00", the microinstruction address is determined by the output of the machine instruction decoding circuit 110. To execute conditional branch instruction 113b, status information of 2 bits selected by a CBC field is coupled to a NMAB (next microinstruction address branch) field by status selection circuit 119.
A nanoinstruction of an address stored in nanoinstruction address register 115 is output from nanomemory 116, which nanoinstruction is then stored in nanoinstruction register 117. Computing unit 118 performs predetermined computations in accordance with this nanoinstruction. Status information, for example, at carry flag, etc., produced by this computation is input to the status selection circuit 119. Status selection circuit 119 selects the status information from the computing unit 118 based on the content of the CBC field of the microinstruction 113b, and then outputs to the next microinstruction address determination circuit 111.
Therefore, in the above-mentioned conventional microprogram control device, machine instructions are converted into microinstruction addresses in the machine instruction decoding circuit 110. Microinstructions corresponding to the next microinstruction address are output from the control memory 112. Accordingly, this conventional device can deal with nanoinstructions common to different machine instructions, which results in reduced memory area. However, a control memory 112 that stores the next microinstruction address portion corresponding to the NMA field is required. In addition, extra time to determine next microinstruction addresses is required by the microcomputer. Thus, the employment of such a conventional microprogram control device results in increased chip area and lower operating speed of the microcomputer.